1. Field of the Invention
This invention relates to an interrupt controller and an interrupt control method. More particularly, embodiments of this invention relate to an interrupt controller and interrupt control method which manage interrupt requests in a low power mode.
2. Description of the Prior Art
In a data processing apparatus, processing logic, for instance a microprocessor, may be responsive to interrupt request signals to interrupt its current operation to service a new operation identified by the interrupt request signals. Handling of these interrupt request signals is usually conducted by an interrupt controller.
For certain applications such as mobile consumer devices, reducing power usage is an important design criterion. In particular, when designing for such applications it is desirable for each component to be configured to save power when not in use. One way of achieving this is to allocate components of a data processing apparatus to different power domains, in dependence on their usage. For instance, a central processing unit CPU could be provided in a first domain which is configured to be powered down to save power when no data or instructions are required to be processed, whereas a memory could be provided in a second domain which is constantly powered to preserve the content of the memory.
In such an arrangement, correct operation of an interrupt controller could be achieved by locating the interrupt controller within the constantly powered domain to ensure that interrupt requests can be handled even when the central processing unit is powered down. The dynamic power consumption of the interrupt controller can in this case be reduced by clock gating when the interrupt controller is not in use, but the static power will still remain due to leakage through the silicon, thereby causing problems for ultra low power designs.